2. Release Notes#

2.1. Changelog#

2.1.1. Spec 13.5#

Supported Architectures#

Added support for f8E4M3FN and f8E5M2 types on Ada (sm_89).

New Operations#

(--preview=simt only) Added op cuda_tile.preview$call to invoke SIMT library functions from within CUDA Tile IR kernels. This feature is currently in preview and is not portable to future versions. Please see the documentation for details.
Added op cuda_tile.multimem_load_reduce_view_tko to load and reduce corresponding elements across a multicast-backed tile view, returning the reduced tile. (Supported for multicast-backed cuda_tile.partition_view on sm_100, sm_103, and sm_107, when GPUs are connected through an NVSwitch fabric with NVLink SHARP support.)
Added op cuda_tile.multimem_reduce_view_tko to atomically reduce an input tile elementwise into each destination associated with a multicast-backed view. (Supported for multicast-backed cuda_tile.partition_view on sm_100, sm_103, and sm_107, when GPUs are connected through an NVSwitch fabric with NVLink SHARP support.)
Added op cuda_tile.multimem_store_view_tko to store the same tile to each destination of a multicast-backed view. (Supported for multicast-backed cuda_tile.partition_view on sm_100, sm_103, and sm_107, when GPUs are connected through an NVSwitch fabric with NVLink SHARP support.)

Modified Operations#

Modified op cuda_tile.atomic_red_view_tko to add the inbounds boolean array attribute, allowing programs to guarantee that the indicated dimensions are always in-bounds and permitting the compiler to omit generating bounds checks for those dimensions.
Modified op cuda_tile.atomic_red_view_tko to now accept views carrying padding_value.

New and Modified Attributes#

Added multimem_reduction_kind attribute with add, min, max, umin, umax, and, or, and xor variants.
Modified attribute ptr_attr to add unicast and multicast variants to represent pointers to memory across multiple GPUs. The classification carries over to a tile view created from the pointer. unicast denotes peer-to-peer access over NVLink; unicast-backed views are supported in normal view-based memory operations. multicast denotes one-to-many and additionally requires an NVSwitch fabric with NVLink SHARP support. Memory accesses through multicast-backed views must use explicit multimem operations. These pointers must be created externally and passed to CUDA Tile IR kernels; please see the documentation for details.

Compiler Improvements#

Added a new opt-in optimization remark indicating when the compiler is not able to automatically narrow a tensor view index to i32. See Compiler Optimization Remarks.
Added a warning for unusually high estimated per-thread register usage to help identify excessive compilation times, with suggestions to reduce tile size or lower the occupancy hint.
Introduced new preview classification for compiler features. Preview features are unstable, not compatible across versions, and always explicitly opt-in. The debut preview category, simt, allows calling SIMT-implemented library functions and requires explicit enablement with --preview=simt. Please see the documentation for details.
Optimization hint num_worker_warps_per_cta now accepts any power of two value from 1 to 32 (formerly only accepted 4 and 8).

Documentation Improvements#

Clarified floating point behavior in several places, including strict widening conversions for cuda_tile.ftof, sign-preserving flush-to-zero behavior, and the lack of bit-identical MMA results when changing across programs, toolchains, or architectures. See Floating-Point Conversion Semantics and MMA Numerical Stability.
Clarified the f4E2M1FN memory access contract and explicitly detailed view conventions required for access to be well-formed. See Sub-Byte Types.
Expanded token ordering documentation with examples of races caused by missing dependencies and legal reordering of independent weak memory accesses. See Hazards and intuition in the CUDA Tile IR Memory Model.
Improved documentation for Rubin shared-memory configuration requirements, including the oversized shared-memory opt-in and its effect on runtime occupancy.

2.2. Known Issues#

A cuda_tile.loop or cuda_tile.for operation may fail compilation or produce incorrect results when a tile produced by a load is carried between iterations. The issue may occur when the next iteration’s tile is loaded before the carried tile’s final use. As a workaround, place the next load after the carried tile’s final use, or restructure the loop so the loaded tile is not carried between iterations.
Converting a tf32 tile loaded from global memory to f32 may produce incorrect values if the lower 13 mantissa bits of any loaded value are nonzero. These bits do not affect MMA operations on the loaded tile; the issue becomes observable only after conversion to f32. As a workaround, ensure that the lower 13 mantissa bits of every tf32 value loaded from global memory are zero.
An indexing signedness issue can cause miscompilation to TMA for view-based memory operations when the underlying tensor has a large number of elements. Loading or storing to a view whose underlying cuda_tile.tensor_view has 2^31 elements or more along a single dimension can trigger the miscompilation. As a workaround, limit the size of tensors to 2^31-1 per dimension, or set the allow_tma optimization hint to false on affected loads and stores.
The specifications of cuda_tile.scan and cuda_tile.reduce implicitly allow several behaviors that are not yet fully supported. The body of a scan or reduce op capturing SSA values from an enclosing scope, using non-scalar intermediate tiles, or nesting region-bearing operations may cause miscompilation.
Floating-point atomic addition (addf) in cuda_tile.atomic_rmw_tko and cuda_tile.atomic_red_view_tko currently flushes subnormal values to zero. This behavior is not intended and is expected to change in a future compiler version; programs should not rely on it.