Best Computer Architecture Books: Code to Hennessy and Patterson

Most programmers carry a model of the CPU that stopped being true decades ago: instructions run one after another, and every memory access costs about the same. The best computer architecture books exist to break that model, and they do it from opposite ends. Charles Petzold’s Code starts with a flashlight and a relay and ends with a working processor. Hennessy and Patterson’s Computer Architecture: A Quantitative Approach assumes you already know what a pipeline is and asks how much each design choice really buys you.

Original content from computingforgeeks.com - post 182523

We picked nine books that cover the whole climb, from logic gates through RISC-V datapaths to caches, GPUs and domain-specific accelerators, and matched each one to where you’re starting. Every edition, page count and price band was checked against the publisher and the Amazon catalog in November 2026. The cache numbers in the lab section come from an Ubuntu 24.04 VM we ran the books’ own experiments on.

What to read first, by starting point

Start with Code if you have never thought about how a transistor becomes an adder, and start with Computer Organization and Design if you can already read a little assembly and want the real course material. The jump between those two is the one that matters, because the textbook assumes the mental model that Petzold spends 480 pages building. These are the picks for each starting point:

• Best first book: Code, 2nd Edition. It builds a CPU from relays and gates in plain prose, with no prerequisites.
• Best hands-on build: The Elements of Computing Systems, 2nd Edition. Twelve projects take you from a Nand gate to a computer running Tetris, with free tools.
• Best course textbook: Computer Organization and Design RISC-V Edition, 2nd Edition. The standard undergraduate text, built on an open instruction set.
• Best advanced reference: Computer Architecture: A Quantitative Approach, 7th Edition. Memory hierarchy, parallelism and accelerators, argued with numbers.
• Best for working programmers: Write Great Code, Volume 1. How the machine sees your data, with no assembly required.
• Best free option: Dive Into Systems. The full text is free online, and the paperback is there if you’d rather read on paper.

If you only buy one book, buy the one that matches your next step rather than the most famous one. Plenty of people order the Quantitative Approach because it has the biggest reputation, then stall in chapter two because it treats cache basics as review. Those basics sit in a printed appendix, and the main text assumes you learned them from its sister volume first.

How we chose the nine books

We started from the searches readers actually make (beginners, modern architecture, RISC-V, the Patterson and Hennessy pair) and from each publisher catalog, then kept only titles that are in print as a paperback today. Every edition, page count and publication date comes from the publisher page or the Amazon catalog data we pulled on 1 November 2026, and each cover you see matches the edition we link. Three tests decided what stayed:

• Current edition: the edition we link is the newest one in print, so you do not pay for a book whose examples target a retired instruction set.
• A clear level: the book says who it is for and stays at that level, rather than jumping from gates to superscalar issue in one chapter.
• Something to run: it ships exercises, simulators or code you can work through, because architecture only sticks once you have watched a design fail.

We left out William Stallings’ Computer Organization and Architecture because the only new 11th edition copy we could find on Amazon in November 2026 was the Pearson Global Edition, in scarce stock at a list price of $150. The US printing of the 10th edition was listed near $279. Computer Systems: A Programmer’s Perspective also isn’t here, since it is really a systems programming book and already sits in our operating systems book guide. Architecture sits below the languages you write, so this list is the hardware layer of our best programming books hub.

How the nine books compare

The two columns that rule books in or out fastest are the level and the instruction set each one teaches on, so read those first:

Book	Level	Instruction set	Published	Pages	Best for
Code, 2nd Ed.	Beginner	None (builds its own CPU)	2022	480	First book
The Elements of Computing Systems, 2nd Ed.	Beginner to intermediate	Hack (16-bit teaching ISA)	2021	344	Building a computer
Computer Organization and Design RISC-V, 2nd Ed.	Undergraduate	RISC-V	2020	736	The core course
Computer Architecture: A Quantitative Approach, 7th Ed.	Graduate	ISA-neutral, RISC-V examples	2025	936	Design trade-offs
Digital Design and Computer Architecture, RISC-V Ed.	Undergraduate	RISC-V	2021	592	HDL and FPGA work
Write Great Code, Vol. 1, 2nd Ed.	Working programmer	Generic, some x86 and ARM	2020	472	Performance intuition
Dive Into Systems	Undergraduate	x86-64, IA32, ARM64	2022	816	Free systems text
Modern Computer Architecture and Organization, 2nd Ed.	Intermediate	x86, x64, ARM, RISC-V	2022	666	Survey of current designs
But How Do It Know?	Beginner	Teaching 8-bit design	2009	222	The shortest path in

RISC-V dominates the teaching texts now, and that’s a deliberate choice by the authors, not a fashion. The ISA is small enough that a student can hold the whole base instruction set in their head, and it is open, so the simulators and FPGA cores the books rely on are free. If your day job is x86 or ARM, do not let that put you off. The concepts carry over, and our lab section shows the same loop compiled for both.

1. Code: The Hidden Language of Computer Hardware and Software, 2nd Edition

Charles Petzold’s book is the one we’d hand anyone who asks how a computer really works, because it never asks you to take a step on faith. It starts with Morse code and Braille, moves through relays and logic gates to binary adders and memory, and ends with a processor you have watched get built one circuit at a time. The second edition adds chapters on the arithmetic logic unit, registers and busses, CPU control signals, and jumps, loops and calls, which closes the gap the 1999 edition left between a single gate and a running program.

It suits self-taught developers, career changers and anyone who wants the intuition before the formalism. Petzold built an animated companion site, CodeHiddenLanguage.com, where the circuits from the book switch as you click, and it is worth keeping open while you read the middle chapters. Look elsewhere if you need course material: there are no exercises, no pipelining and no caches, so it prepares you for a textbook rather than replacing one.

The second edition came out from Microsoft Press in July 2022 at 480 pages. The paperback was running about $32 to $40 in November 2026, so check the current price on Amazon before you order.

2. The Elements of Computing Systems, 2nd Edition

Noam Nisan and Shimon Schocken wrote the book behind the nand2tetris course, and it is the best way we know to learn architecture by building it. You start with a single Nand gate, describe every other gate in a simple hardware description language, then assemble an ALU, RAM, a CPU and finally a complete 16-bit computer called Hack. The second half climbs back up through an assembler, a virtual machine, a compiler and a small operating system, so by project twelve you have written every layer between the gate and Tetris yourself.

The hardware simulator, CPU emulator and project files are free on nand2tetris.org, and the lectures run as a course on Coursera, so the book is the spine of a full self-study track. It fits programmers who learn by doing and want the satisfaction of a machine that actually boots. The Hack CPU has no pipeline, no cache and no interrupts, which keeps it buildable but means you’ll still need Patterson and Hennessy for how real processors chase performance.

MIT Press published the second edition in June 2021 at 344 pages, reorganized into two parts of six projects each. The first edition from 2005 is still listed, so make sure the cover says Second Edition. New copies were about $40 to $60 in November 2026, with stock marked scarce, so check the live price on Amazon.

3. Computer Organization and Design RISC-V Edition, 2nd Edition

David Patterson and John Hennessy’s Computer Organization and Design is the textbook most universities teach from, and the RISC-V edition is the one to buy now. It walks from instructions and arithmetic through the datapath of a single-cycle and then a pipelined RISC-V processor, then spends a long chapter on the memory hierarchy and closes with parallel processors from phones to warehouse-scale clusters. The second edition adds a domain-specific architecture section to every chapter, so the book reaches the accelerator designs that matter for machine learning hardware.

This is the book to read if you want the real undergraduate course, whether you’re enrolled or teaching yourself. The editions confuse people. On Amazon today the RISC-V 2nd edition (December 2020) is the current one, and there is no RISC-V 3rd edition. The MIPS 6th edition came out the same season, and the ARM edition dates from 2016. Don’t pick it as a first book if you have never seen assembly. The second chapter teaches RISC-V instructions fast, and our assembly language books guide covers gentler starts.

Morgan Kaufmann’s paperback runs 736 pages and was listed near $99 in November 2026, with scarce stock. Check the current price on Amazon, because textbook prices swing hard around semester starts.

4. Computer Architecture: A Quantitative Approach, 7th Edition

The Quantitative Approach is the graduate-level sister of the previous book, and its whole method is in the title: every design idea is judged by what it does to performance, power and cost, with real measurements. The seventh edition adds Christos Kozyrakis as a third author and keeps the familiar structure. Its chapters cover quantitative design, the memory hierarchy, instruction-level parallelism, data-level parallelism across vector, SIMD and GPU designs, thread-level parallelism, warehouse-scale computers and domain-specific architectures. GPU, CPU and system-on-chip coverage was updated for this edition, which matters because the 2017 sixth edition predates most of today’s AI accelerators.

It’s written for graduate students, chip designers and performance engineers who already know what a pipeline hazard is. The printed appendices review instruction set principles, the memory hierarchy and pipelining, and appendices D through M live online, so the book doesn’t strand you if your undergraduate memory is rusty. Don’t make it your first architecture book, though: it moves at the pace of a graduate seminar and assumes Computer Organization and Design as background.

Elsevier dates the seventh edition December 2025, and the Amazon listing gives it 936 pages. Amazon showed it in November 2026 at about $69 to $110 with a lead time before shipping, so if you need it this week, the sixth edition is still in stock at a similar page count. Check the current price and delivery date on Amazon.

5. Digital Design and Computer Architecture, RISC-V Edition

Sarah Harris and David Harris start one level lower than Patterson and Hennessy, at the digital logic itself, and climb until you have built a RISC-V processor in a hardware description language. Every design comes in both SystemVerilog and VHDL, and the processor chapter builds single-cycle, multicycle and pipelined versions of the same core, so you see exactly what pipelining costs in hardware. A bonus chapter on I/O systems lives on the companion website and uses a real SparkFun RED-V board, and the same site carries labs, slides and links to the free CAD tools the exercises use.

Pick this one if you’re heading toward FPGA work, chip design or embedded hardware, because no other book on the list makes you write the processor in a language a synthesis tool accepts. Software developers who only want to understand performance will find the logic chapters slow going, and they’d get more from Write Great Code or the free systems text at pick 7.

The RISC-V edition was published by Morgan Kaufmann in October 2021 at 592 pages. It sold for about $69 to $100 in November 2026 with stock marked scarce, so check the live price on Amazon.

6. Write Great Code, Volume 1: Understanding the Machine, 2nd Edition

Randall Hyde wrote this one for high-level programmers who want to know why some code is fast, and it asks for no assembly at all. It covers how integers, floating-point numbers and characters are stored, how memory is organized, enough boolean logic and digital design to explain a CPU, and then the instruction set, memory architecture, I/O, buses and mass storage. The second edition adds 64-bit code generation, ARM on phones and tablets, SSDs, and examples in Swift and Java.

It’s the right pick for working developers in C, C++, Rust or Go who keep hearing about cache misses and alignment but never had the course. Each chapter ties the hardware fact back to a decision you make in code, which is the part the textbooks leave as an exercise. Students in a formal architecture class should look past it, since there’s no datapath design and no problem sets.

No Starch Press published the second edition in August 2020 at 472 pages, and it pairs well with our C and C++ books list if those are your working languages. The paperback ran about $34 to $50 in November 2026, so check the current price on Amazon.

7. Dive Into Systems

Suzanne Matthews, Tia Newhall and Kevin Webb wrote this book as a free textbook, and the No Starch paperback is the same material in print. It starts with C, gdb and Valgrind, then moves through binary representation and assembly in three flavors (64-bit x86, 32-bit x86 and 64-bit ARM). Later chapters cover architecture, the memory hierarchy and caching, an introduction to operating systems and shared-memory parallelism with pthreads. Because it shows the same programs in all three assemblies, it is the gentlest way on this list to see how much of architecture is independent of the instruction set.

Read it at diveintosystems.org before you spend anything, and buy the paperback only if you’d rather annotate on paper. It suits students and self-learners who want architecture and systems programming in one book. It goes less deep on processor design than Patterson and Hennessy, so treat it as the bridge between your code and their datapaths rather than a replacement.

No Starch printed it in 2022 at 816 pages. It was listed at about $52 to $80 in November 2026 with scarce stock, so check the live price on Amazon.

8. Modern Computer Architecture and Organization, 2nd Edition

Jim Ledin’s book is a survey of how current processors and systems are put together, across x86, x64, ARM and RISC-V rather than one teaching ISA. It has a full chapter on the RISC-V architecture and instruction set, another on processor virtualization, a project that implements a RISC-V processor on a low-cost FPGA, and a quantum computing program you can run on real hardware. The second edition adds chapters on cybersecurity and confidential computing, blockchain and bitcoin mining, and self-driving vehicle architectures.

Engineers who want breadth and current examples will get the most from it, especially if they want to know why a phone SoC, a server CPU and a GPU look so different. The code for every chapter lives in the Packt GitHub repository. Its breadth is also its limit: no single topic gets the rigor of the Morgan Kaufmann texts, so pair it with one of them if you need depth on pipelines or caches.

Packt published the second edition in May 2022 at 666 pages. The paperback sold for anywhere from about $39 to its $90 list price in November 2026, so check the current price on Amazon.

9. But How Do It Know? The Basic Principles of Computers for Everyone

J. Clark Scott’s self-published book is the shortest route on this list from “what is a bit” to a working CPU. In 222 pages it builds memory, an ALU and a simple 8-bit computer out of gates, then shows how a stored program walks through that machine one step at a time. It covers less ground than Code and skips the history, which is exactly why some readers finish it in a weekend after giving up on longer books.

It’s for complete beginners, including non-programmers, and for anyone who wants a quick primer before nand2tetris. Since it is self-published, there’s no publisher review behind it, and the 2009 text says nothing about caches, pipelines or multicore chips. The old companion website no longer loads either, so the book is all you get.

The paperback is still in print at about $19 to $20 as of November 2026, so check the current price on Amazon.

What a cache miss costs on a real CPU

A load that misses every cache costs about a hundred times more than one that hits L1, and you can measure that yourself in ten minutes. Every book above leans on that gap, so we ran the classic experiments to show what the numbers look like before you read the theory. The lab was an Ubuntu 24.04 VM with 4 vCPUs on an Intel Core i7-1165G7 host, passed through with the host CPU type. Install a compiler, the RISC-V cross toolchain, the QEMU user-mode emulator and perf. The linux-tools package only exists for Ubuntu-built kernels, so drop it from the line if you run a custom kernel:

sudo apt update
sudo apt install -y build-essential gcc-riscv64-linux-gnu qemu-user linux-tools-common linux-tools-$(uname -r)

Start by asking the machine what it thinks its caches are. The kernel exposes the cache geometry through lscpu, getconf and sysfs:

lscpu | grep -E 'Model name|Architecture|^CPU\(s\)|L1d|L1i|L2|L3|Thread|Core'
getconf -a | grep -i CACHE

Our VM reported a 32 KiB, 8-way L1 data cache per core with 64-byte lines. Only the line size is right, and the L2 and L3 lines are even further off:

lscpu says the L2 is 4 MiB per core and the L3 is 16 MiB, while getconf says the L2 is 2 MiB. Neither is right. Intel lists the i7-1165G7 with 12 MB of cache, and its Willow Cove cores carry a 48 KiB, 12-way L1 data cache and 1.25 MiB of L2 each. The hypervisor is passing the guest cache descriptors that do not describe the silicon. The sysfs view tells the same story, with associativity added:

grep . /sys/devices/system/cpu/cpu0/cache/index*/{level,type,size,coherency_line_size,ways_of_associativity}

Run that under bash, since plain sh won’t expand the braces. Each index directory is one cache, and the ways_of_associativity files are the set-associativity that the memory hierarchy chapters teach:

That mismatch is the first lesson of the Quantitative Approach in miniature: do not trust the label, measure the machine. A virtual machine is the common case for anyone reading this in the cloud, so the reported sizes are a hint, and the latency curve below is the fact.

How the pointer-chase benchmark finds each cache level

The trick is to make every load depend on the one before it, so the CPU can’t overlap them, and to visit memory in a random cycle, so the prefetcher can’t guess the next address. Time 50 million of those loads over a growing buffer, and the average cost per load jumps each time the buffer outgrows a cache. Create the program:

vim walk.c

Paste this source, which builds a random cyclic permutation of pointers for each buffer size and then chases it:

#include <stdio.h>
#include <stdlib.h>
#include <time.h>

static double now(void) {
    struct timespec t;
    clock_gettime(CLOCK_MONOTONIC, &t);
    return t.tv_sec + t.tv_nsec * 1e-9;
}

int main(void) {
    size_t kib[] = {4, 16, 32, 64, 256, 1024, 4096, 16384, 65536, 262144};
    const long loads = 50000000;
    srand(42);
    puts("size_kib ns_per_load");
    for (int s = 0; s < 10; s++) {
        size_t n = kib[s] * 1024 / sizeof(void *);
        void **buf = malloc(n * sizeof(void *));
        size_t *idx = malloc(n * sizeof(size_t));
        for (size_t i = 0; i < n; i++) idx[i] = i;
        for (size_t i = n - 1; i > 0; i--) {
            size_t j = (((size_t)rand() << 31) ^ rand()) % (i + 1);
            size_t t = idx[i]; idx[i] = idx[j]; idx[j] = t;
        }
        for (size_t i = 0; i < n; i++) buf[idx[i]] = &buf[idx[(i + 1) % n]];
        void **p = &buf[idx[0]];
        for (long i = 0; i < n; i++) p = *p;
        double t0 = now();
        for (long i = 0; i < loads; i++) p = *p;
        double t1 = now();
        printf("%zu %.2f\n", kib[s], (t1 - t0) / loads * 1e9);
        if (p == NULL) puts("never");
        free(buf); free(idx);
    }
    return 0;
}

Compile it with optimization on and run it. The whole sweep takes about 35 seconds:

gcc -O2 -o walk walk.c
./walk

Read the second column as nanoseconds per load, and watch where it jumps:

Up to 32 KiB every load costs about 1.3 ns, because the whole buffer fits in the 48 KiB L1. At 64 KiB it rises to about 2 ns, which is L1 spilling into L2. It keeps climbing to 5.5 ns at 1 MiB as the buffer fills the 1.25 MiB L2. At 4 MiB the loads come from L3, and from 16 MiB up they come from DRAM at 108 to 137 ns, roughly a hundred times the L1 cost. A second run gave the same shape with one noisy point: the 4 MiB step read 25.9 ns the first time and 14.8 ns the second, because the Proxmox node was busy with other lab VMs and they share the host L3. That is why the books tell you to repeat a measurement before you believe it.

Why the same loop runs 30 times slower by column

Access order matters as much as data size, and a 4096 by 4096 matrix of ints makes that visible. C stores the matrix row by row, so summing it along rows reads memory in order, while summing it along columns jumps 16 KiB between loads. Create rowcol.c with vim rowcol.c and add:

#include <stdio.h>
#include <stdlib.h>
#include <time.h>

#define N 4096

static double now(void) {
    struct timespec t;
    clock_gettime(CLOCK_MONOTONIC, &t);
    return t.tv_sec + t.tv_nsec * 1e-9;
}

int main(void) {
    int (*m)[N] = malloc(sizeof(int[N][N]));
    for (int i = 0; i < N; i++)
        for (int j = 0; j < N; j++) m[i][j] = i ^ j;

    volatile long sink;
    double t0 = now();
    long a = 0;
    for (int i = 0; i < N; i++)
        for (int j = 0; j < N; j++) a += m[i][j];
    sink = a;
    double t1 = now();
    long b = 0;
    for (int j = 0; j < N; j++)
        for (int i = 0; i < N; i++) b += m[i][j];
    sink = b;
    double t2 = now();

    printf("row-major:    %.3f s (sum %ld)\n", t1 - t0, a);
    printf("column-major: %.3f s (sum %ld)\n", t2 - t1, b);
    return 0;
}

Build and run it:

gcc -O2 -o rowcol rowcol.c && ./rowcol

Both loops add the same 16.8 million numbers and print the same sum, yet the column walk took 0.147 s against 0.005 s for the row walk:

Part of that gap of about 30 times may be the compiler, since GCC is free to vectorize the row loop with SIMD loads (we did not check its vectorizer report). The bigger part is the memory system, and the hardware counters prove it. As a normal user, perf refused to read them because perf_event_paranoid was set to 4 on this VM, with “Access to performance monitoring and observability operations is limited”, so run it with sudo:

sudo perf stat -e cache-references,cache-misses,L1-dcache-load-misses ./rowcol

We ran the same command from a root shell, and the counters worked inside the VM:

The counters cover the whole program, and they read 17.2 million cache misses. The setup pass and the row walk each touch the 64 MiB matrix in order, so they miss only once per 64-byte line, about a million times each. That leaves roughly 15 million misses for the 16.8 million loads of the column walk. Most of those loads missed the last-level cache. The column walk lands on a new line and a new 4 KiB page with every load, and with a power-of-two stride those lines compete for the same few cache sets, so they’re evicted before the next column comes back for them. Hennessy and Patterson call those conflict misses, and the memory hierarchy chapter in either of their books is where the fix (loop interchange or blocking) comes from.

What the same loop looks like in RISC-V and x86-64

Most of the textbooks above teach on RISC-V while most readers run x86-64, so it helps to see one small function in both. Create sum.c with vim sum.c; the MAIN block only exists so the RISC-V build has something to run:

long sum(const int *a, long n) {
    long s = 0;
    for (long i = 0; i < n; i++)
        s += a[i];
    return s;
}

#ifdef MAIN
#include <stdio.h>
int main(void) {
    int a[1000];
    for (int i = 0; i < 1000; i++) a[i] = i;
    printf("sum = %ld\n", sum(a, 1000));
    return 0;
}
#endif

Ask the RISC-V cross compiler for assembly instead of an object file:

riscv64-linux-gnu-gcc -O2 -S -o - sum.c

Trimmed to the function body (the full listing adds assembler directives), GCC 13.3 produced this:

sum:
	ble	a1,zero,.L4
	slli	a1,a1,2
	mv	a5,a0
	add	a3,a0,a1
	li	a0,0
.L3:
	lw	a4,0(a5)
	addi	a5,a5,4
	add	a0,a0,a4
	bne	a5,a3,.L3
	ret
.L4:
	li	a0,0
	ret

The native compiler gives the x86-64 version of the same loop:

gcc -O2 -S -o - sum.c

Again trimmed to the function, it reads:

sum:
	endbr64
	testq	%rsi, %rsi
	jle	.L4
	leaq	(%rdi,%rsi,4), %rcx
	xorl	%eax, %eax
.L3:
	movslq	(%rdi), %rdx
	addq	$4, %rdi
	addq	%rdx, %rax
	cmpq	%rcx, %rdi
	jne	.L3
	ret
.L4:
	xorl	%eax, %eax
	ret

The RISC-V inner loop is four instructions and the x86-64 one is five, and the difference is a textbook point. In RISC-V, bne compares two registers and branches in one instruction, while x86 sets flags with cmpq and branches on them with jne. The RISC-V lw already sign-extends the 32-bit int into a 64-bit register, the same job x86 does with movslq. Chapter two of Computer Organization and Design spends its pages on exactly these choices. Finally, build a static RISC-V binary and run it under QEMU’s user-mode emulator:

riscv64-linux-gnu-gcc -O2 -static -DMAIN -o sum-rv sum.c && file sum-rv && qemu-riscv64 ./sum-rv

file confirms a 64-bit RISC-V executable with the compressed (RVC) extension, and QEMU prints the right sum of 0 through 999:

That setup is all the RISC-V textbooks need for their programming exercises, so you do not have to buy a board to follow them. The toolchain versions on our VM were GCC 13.3.0 for both targets and QEMU 8.2.2.

How to order the reading

The books stack, and reading them out of order is the most common reason people give up. A self-taught path that works for most readers goes like this:

1. Code (or But How Do It Know? if you want the short version) for the model of gates, memory and a CPU.
2. The Elements of Computing Systems, building the projects, so the model turns into something you have made work.
3. Computer Organization and Design RISC-V Edition for pipelines, caches and the real course material, with the free Matthews, Newhall and Webb systems text beside it if you want more C and assembly practice.
4. Computer Architecture: A Quantitative Approach once you want to argue about design choices with numbers.

Branch off at step three depending on where you’re heading. Hardware and FPGA people should add Digital Design and Computer Architecture, working programmers get more from Write Great Code, and anyone who wants a tour of current designs should add Ledin. From there, our Linux kernel programming books pick up where the architecture leaves off, and the CUDA books take the data-level parallelism chapter onto a real GPU.

What these books correct about CPUs

The lab numbers above make the case better than any review could, and they line up with the beliefs these books spend the most pages taking apart:

• “A faster CPU makes everything faster”: once your data outgrows the caches, the core spends most of its time waiting on DRAM, which our walk showed at more than 100 ns a load against 1.3 ns from L1.
• “Big-O is the whole story”: the row and column loops are the same O(n²) algorithm, yet one ran about 30 times slower because of the order it touched memory.
• “Architecture means learning one instruction set”: the four-instruction RISC-V loop and the five-instruction x86 loop do the same work, and what transfers between them is the model of registers, memory and branches.

If one of those surprised you, start with the book that matches your level and keep the lab programs around. Rerunning walk.c on your own laptop or a cloud instance is the fastest way to check what you have read against the machine in front of you, especially if you’re sizing hardware like the picks in our home server CPU guide.